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FDS8874 N-Channel PowerTrench(R) MOSFET
August 2005
FDS8874 N-Channel PowerTrench(R) MOSFET
30V, 16A, 5.5m Features
rDS(ON) = 5.5m, VGS = 10V, ID = 16A rDS(ON) = 7.0m, VGS = 4.5V, ID = 15A High performance trench technology for extremely low rDS(ON) Low gate charge High power and current handling capability 100% Rg tested RoHS Compliant
General Description
This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed.
5 6 7 8
4 3 2 1
MOSFET Maximum Ratings
Symbol VDSS VGS ID EAS PD TJ, TSTG Drain to Source Voltage Gate to Source Voltage Drain Current
TA = 25C unless otherwise noted Parameter Ratings 30 20 16 15 Figure 4 265 2.5 20 -55 to 150 Units V V A A A mJ W mW/oC
o
Continuous (TA = 25oC, VGS = 4.5V, RJA = 50oC/W) Pulsed Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature
Continuous (TA = 25oC, VGS = 10V, RJA = 50oC/W)
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance, Junction to Case (Note 2) Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 25 50 85
o
C/W C/W
oC/W o
Package Marking and Ordering Information
Device Marking FDS8874 Device FDS8874 Package SO-8
1
Reel Size 330mm
Tape Width 12mm
Quantity 2500 units
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(c)2005 Fairchild Semiconductor Corporation FDS8874 Rev. A
FDS8874 N-Channel PowerTrench(R) MOSFET
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 24V VGS = 0V VGS = 20V TA = 150oC 30 1 250 100 V A nA
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 16A, VGS = 10V ID = 15A, VGS = 4.5V ID = 16A, VGS = 10V, TA = 150oC 1.2 0.0056 2.5 0.007 V 0.0045 0.0055 0.0078 0.0102
Dynamic Characteristics
CISS COSS CRSS RG Qg Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge Total Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 15V, VGS = 0V, f = 1MHz f = 1MHz VGS = 10V VGS = 5V VDD = 15V ID = 16A 0.4 3000 600 350 1.6 56 30 8.0 5.0 10 3990 800 525 4.0 72 38 pF pF pF nC nC nC nC nC
Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID = 16A VGS = 10V, RGS = 4.7 9 45 54 20 81 111 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 16A ISD = 2.1A ISD = 16A, dISD/dt = 100A/s ISD = 16A, dISD/dt = 100A/s 1.25 1.0 28 13 V V ns nC
Notes: 1: Starting TJ = 25C, L = 1mH, IAS = 23A, VDD = 30V, VGS = 10V. 2: RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RJA is determined by the user's board design. 3: RJA is measured with 1.0 in2 copper on FR-4 board
2 FDS8874 Rev. A
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FDS8874 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TA = 25C unless otherwise noted
1.2 1.0 ID, DRAIN CURRENT (A) 15 VGS = 4.5V 10 VGS = 10V 0.8 0.6 0.4 0.2 RJA=50oC/W 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 20
POWER DISSIPATION MULTIPLIER
5
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Ambient Temperature
RJA=50oC/W
ZJA, NORMALIZED THERMAL IMPEDANCE
0.1
PDM t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 102 103
0.01
0.001 10-5 10-4 10-3
Figure 3. Normalized Maximum Transient Thermal Impedance
2000 1000 IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
VGS = 4.5V VGS = 10V 100
TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103
Figure 4. Peak Current Capability
3 FDS8874 Rev. A
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FDS8874 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TA = 25C unless otherwise noted
100 IAS, AVALANCHE CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID , DRAIN CURRENT (A) 50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V TJ = 25oC 30
40
10
STARTING TJ = 25oC
20 TJ = 150oC 10 TJ = -55oC
STARTING TJ = 150oC
1 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms)
0 1.5
2.0
2.5
3.0
VGS , GATE TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Unclamped Inductive Switching Capability
Figure 6. Transfer Characteristics
50 VGS = 10V 40. ID, DRAIN CURRENT (A) VGS = 5V 30 VGS = 3V VGS = 4V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
14 ID = 16A 12 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
10
20
VGS = 2.5V TA = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0.1 0.2 0.3 0.4
8
10
6
0 VDS , DRAIN TO SOURCE VOLTAGE (V)
4 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Gate Voltage and Drain Current
1.4
1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE 1.4
VGS = VDS, ID = 250A 1.2
1.2
1.0
1.0
0.8
0.8 VGS = 10V, ID = 16A 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.6
0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature
4 FDS8874 Rev. A
Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature
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FDS8874 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TA = 25C unless otherwise noted
1.10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.05 CISS = CGS + CGD C, CAPACITANCE (pF) COSS CDS + CGD 1000 CRSS = CGD 5000
1.00
0.95
0.90 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
VGS = 0V, f = 1MHz 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30
Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V)
Figure 12. Capacitance vs Drain to Source Voltage
VDD = 15V
8
6
4
2
WAVEFORMS IN DESCENDING ORDER: ID = 16A ID = 1A 0 10 20 30 40 50 60
0 Qg, GATE CHARGE (nC)
Figure 13. Gate Charge Waveforms for Constant Gate Currents
5 FDS8874 Rev. A
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FDS8874 N-Channel PowerTrench(R) MOSFET
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG
+
BVDSS VDS VDD
VDD -
0V
IAS 0.01
0 tAV
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
VDS
VDD L
Qg(TOT) VDS VGS VGS = 10V Qg(5)
VGS
+
DUT Ig(REF)
VDD
Qgs2
VGS = 5V
VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
6 FDS8874 Rev. A
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FDS8874 N-Channel PowerTrench(R) MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P = -----------------------------DM RJA
maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 64 + -------------------------------
26 0.23 + Area
(EQ. 2)
(EQ. 1)
In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized
150 120 90 60 30 0 10-1 100 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2
The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
200 RJA = 64 + 26/(0.23+Area)
RJA (oC/W)
150
100
50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10
Figure 21. Thermal Resistance vs Mounting Pad Area
ZJA, THERMAL IMPEDANCE (oC/W)
101 t, RECTANGULAR PULSE DURATION (s)
102
103
Figure 22. Thermal Impedance vs Mounting Pad Area
7 FDS8874 Rev. A
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FDS8874 N-Channel PowerTrench(R) MOSFET
PSPICE Electrical Model
.SUBCKT FDS8874 2 1 3 ; Ca 12 8 2.4e-9 Cb 15 14 2.4e-9 Cin 6 8 2.6e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 33.5 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 4e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1e-10 RLgate 1 9 40 RLdrain 2 5 10 RLsource 3 7 1 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.35e-3 Rgate 9 20 1.9 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} .MODEL DbodyMOD D (IS=7E-12 IKF=10 N=1.01 RS=2.5e-3 TRS1=8e-4 TRS2=2e-7 + CJO=1.13e-9 M=0.57 TT=1e-15 XTI=1.2) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.13e-9 IS=1e-30 N=10 M=0.4) .MODEL MmedMOD NMOS (VTO=1.8 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9) .MODEL MstroMOD NMOS (VTO=2.2 KP=380 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.49 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=5e-3 TC2=1e-5) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.1e-3 TC2=-8e-6) .MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2.0) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8 FDS8874 Rev. A www.fairchildsemi.com
CA LGATE GATE 1 RLGATE CIN ESG + EVTEMP RGATE + 18 22 9 20 10 RSLC1 51 ESLC 50 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO LSOURCE 8 RSOURCE 12 S1A 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 RLSOURCE SOURCE 3
rev May 2004
DPLCAP
LDRAIN 5 DRAIN 2
5 51
6 8 EVTHRES + 19 8 6
+ -
RSLC2
RDRAIN 21 16
DBODY
FDS8874 N-Channel PowerTrench(R) MOSFET
SABER Electrical Model
REV May 2004 template FDS8874 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=7e-12,ikf=10,nl=1.01,rs=2.5e-3,trs1=8e-4,trs2=2e-7,cjo=1.13e-9,m=0.57,tt=1e-15,xti=1.2) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.13e-9,isl=10e-30,nl=10,m=0.4) m..model mmedmod = (type=_n,vto=1.8,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.2,kp=380,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.49,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3) LDRAIN DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2.0,voff=-0.5) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2.0) RLDRAIN RSLC1 c.ca n12 n8 = 2.4e-9 51 c.cb n15 n14 = 2.4e-9 RSLC2 c.cin n6 n8 = 2.6e-9 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 33.5 spe.eds n14 n8 n5 n8 = 1 GATE 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 4e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1e-10 res.rlgate n1 n9 = 40 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1
CA 12 S1A 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6 MSTRO CIN 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11
DRAIN 2
DBODY
RLGATE
LSOURCE 7 RLSOURCE 18 RVTEMP 19
SOURCE 3
RSOURCE RBREAK
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7 res.rdrain n50 n16 = 2.35e-3, tc1=5e-3,tc2=1e-5 res.rgate n9 n20 = 1.9 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2e-3, tc1=1e-4,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.1e-3,tc2=-8e-6 res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10)) } }
9 FDS8874 Rev. A
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FDS8874 N-Channel PowerTrench(R) MOSFET
SPICE Thermal Model
REV May 2004 FDS8874T Copper Area =1.0 in2 CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25
th
JUNCTION
RTHERM1
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM3
CTHERM3
6
SABER Thermal Model
Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e-3 ctherm.ctherm2 8 7 =5.0e-3 ctherm.ctherm3 7 6 =1.0e-2 ctherm.ctherm4 6 5 =4.0e-2 ctherm.ctherm5 5 4 =9.0e-2 ctherm.ctherm6 4 3 =2e-1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3 rtherm.rtherm1 th 8 =1e-1 rtherm.rtherm2 8 7 =5e-1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 }
2
RTHERM4 5
CTHERM4
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
tl
CASE
TABLE 1. THERMAL MODELS COMPONANT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7 0.52 in2 2.0e-1 1.0 3.0 15 21 31.3 0.76 in2 2.0e-1 1.0 3.0 13 19 29.7 1.0 in2 2.0e-1 1.0 3.0 12 18 25
10 FDS8874 Rev. A
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FDS8874 N-Channel PowerTrench(R) MOSFET
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FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT 4 5 DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR 3 6 CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 8 which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
7 2
2. A critical component is any component of a life support 1 device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
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